HT66F20 datasheet(190/250 Pages) HOLTEK

190 / 250 page

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

HT66FU30/HT66FU40/HT66FU50/HT66FU60

Rev. 1.20

190

June 4, 2010

UART Module Functional Description

The embedded UART Module is full-duplex asynchron-

ous serial communications UART interface that enables

communication with external devices that contain a se-

rial interface. The UART function has many features and

can transmit and receive data serially by transferring a

frame of data with eight or nine data bits per transmis-

sion as well as being able to detect errors when the data

is overwritten or incorrectly framed. Interconnection be-

tween the MCU and the UART module is implemented

by internally connecting the MCU Master SPI interface

to the UART Slave SPI interface. All data transmissions

and receptions between MCU and UART module in-

cluding UART commands are conducted along this in-

terconnected SPI interface. The UART function control

is executed by the MCU using its SPI Master serial inter-

face. The UART module contains its own independent

interrupt which can be used to indicate when a data re-

ception occurs or when a data transmission has termi-

nated.

UART Module Internal Signal

In addition to the TX and RX external pins described

above there are other MCU to UART Module intercon-

necting lines that are described in the following table.

Note that these lines are internal to the device and are

not bonded to external pins.

UART Module SPI Interface

The MCU communicates with the UART Module via an

internal SPI interface. The SPI interface on this device is

comprised of four signals: SCS (SPI Chip Select), SCK

(SPI Clock), SDI (Serial Data Input) and SDO (Serial

Data Output). The SPI master, which is the MCU, as-

serts SCS by pulling it low to start the data transaction

cycle. When the first 8 bits of data are transmitted, SCS

should not return to a high level. Instead, SCS must re-

main at a low level until the whole 16-bit data transaction

is completed. If SCS is de-asserted, that is returned to a

high level before the 16-bit data transaction is com-

pleted, all data bits will be discarded by the UART Mod-

ule SPI slave.

SPI Timing

Both read and write operations are conducted along the

SPI common interface with the following format:

· Write Type Format: 8-bit command input + 8-bit data

input

· Read Type Format: 8-bit command input + 8-bit data

output

To initiate a data transaction, the MCU master SPI

needs to pull SCS to a low level first and then also pull

SCK low. The input data bit on SDI should be stable be-

fore the next SCK rising edge, as the device will latch

the SDI status on the next SCK rising edge. Regarding

the SDO line, the output data bit will be updated on the

SCK falling edge. The master needs to obtain the line

status before the next SCK falling edge.

There are 16 bits of data transmitted and/or received by

the SPI interface for each transaction. Each transaction

consists of a command phase and a data phase. When

SCS is high, the SPI interface is disabled and SDO will

be set to a high impedance state.

After a complete transaction has been implemented,

which requires 16 SCK clock cycles, the master needs

to set SCS to a high level in preparation for the next data

transaction.

For write operations, the device will begin to execute the

command only after it receives a 16-bit serial data se-

quence and when the SCS has been set high again by

the master.

S C K

S D I

S D O

V D D

S C S

I N T

C L K I

G N D

S C K

S D O

S D I

P C K

S C S

V D D

G N D

M C U

R X

T X

P I N T

U A R T

M o d u l e

V D D

MCU to UART Internal Connection

HT66F20 Datasheet(PDF) 190 Page - Holtek Semiconductor Inc

HT66F20 Datasheet(HTML) 190 Page - Holtek Semiconductor Inc

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