TMS320DM647 datasheet(106/181 Pages) TI

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AECLKIN

AECLKOUT

TMS320DM647

TMS320DM648

SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

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E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns

for EMIFA.

Figure 6-20. AECLKOUT Timing for the EMIFA Module

6.10.3.1 Asynchronous Memory Timing

Table 6-43. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1) (2) (3)

(see Figure 6-21 and Figure 6-22)

720, 800, 900, 1100

NO.

UNIT

MIN

MAX

tsu(EDV-A OEH)

Setup time, AEDx valid before AAOE/ASOE high

6.5

th(AOEH-EDV)

Hold time, AEDx valid after AAOE/ASOE high

tsu(ARDY-EKOH)

Setup time, AARDY valid before AECLKOUT low

th(EKOH-ARDY)

Hold time, AARDY valid after AECLKOUT low

tw(ARDY )

Pulse width, AARDY assertion and deassertion

2E + 5

Delay time, from AARDY sampled deasserted on AECLKOUT falling

td(ARDY-HOLD)

to beginning of programmed hold period

Setup time, before end of programmed strobe period by which

tsu(ARDY-HOLD)

AARDY should be asserted in order to insert extended strobe wait

states.

(1)

E = AECLKOUT period in ns for EMIFA

(2)

To specify data setup time, simply program the strobe width wide enough.

(3)

AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E

to specify setup and hold time is met.

Table 6-44. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module(1) (2) (3) (see Figure 6-21 and Figure 6-22)

720, 800, 900, 1100

NO.

PARAMETER

UNIT

MIN

MAX

tosu(SELV-AOEL)

Output setup time, select signals valid to AAOE/ASOE low

RS × E - 1.5

toh(AOEH-SELIV)

Output hold time, AAOE/ASOE high to select signals invalid

RS × E - 1.9

td(EKOH-AOEV)

Delay time, AECLKOUT high to AAOE/ASOE valid

7.28

tosu(SELV-AWEL)

Output setup time, select signals valid to AAWE/ASWE low

WS × E - 1.7

toh(AWEH-SELIV)

Output hold time, AAWE/ASWE high to select signals invalid

WH × E - 1.8

td(EKOH-AWEV)

Delay time, AECLKOUT high to AAWE/ASWE valid

1.3

7.1

(1)

E = AECLKOUT period in ns for EMIFA

(2)

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIFA CE Configuration registers (CEnCFG).

(3)

Select signals for EMIFA include: ACEx, ABE[1:0], AEA[23:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[15:0].

106

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