TMS320DM647 datasheet(125/181 Pages) TI

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TMS320DM647

TMS320DM648

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SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

6.14.3 SPI Electrical Data/Timing

6.14.3.1 Serial Peripheral Interface (SPI) Timing

Table 6-60 assumes testing over recommended operating conditions (see Figure 6-36).

Table 6-60. General Timing Requirements for SPIx Master Modes(1)

NO.

MIN

MAX UNIT

greater of 8P or

tc(SPC)M

Cycle Time, SPICLK, All Master Modes

256P

100 ns

tw(SPCH)M

Pulse Width High, SPICLK, All Master Modes

greater of 4P or 45 ns

tw(SPCL)M

Pulse Width Low, SPICLK, All Master Modes

greater of 4P or 45 ns

Polarity = 0, Phase = 0,

to SPICLK rising

Polarity = 0, Phase = 1,

0.5tc(SPC)M + 4P

Delay, initial data bit valid

to SPICLK rising

td(SIMO_SPC)M

on SPIDO to initial edge on

Polarity = 1, Phase = 0,

SPICLK(2)

to SPICLK falling

Polarity = 1, Phase = 1,

0.5tc(SPC)M + 4P

to SPICLK falling

Polarity = 0, Phase = 0,

from SPICLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits

from SPICLK falling

td(SPC_SIMO)M

valid on SPIDO after

Polarity = 1, Phase = 0,

transmit edge of SPICLK

from SPICLK falling

Polarity = 1, Phase = 1,

from SPICLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)M - 10

from SPICLK falling

Polarity = 0, Phase = 1,

Output hold time, SPIDO

0.5tc(SPC)M - 10

from SPICLK rising

valid after

toh(SPC_SIMO)M

receive edge of SPICLK,

Polarity = 1, Phase = 0,

0.5tc(SPC)M - 10

except for final bit(3)

from SPICLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)M - 10

from SPICLK falling

Polarity = 0, Phase = 0,

0.5P + 15

to SPICLK falling

Polarity = 0, Phase = 1,

0.5P + 15

Input Setup Time, SPIDI

to SPICLK rising

tsu(SOMI_SPC)M

valid before

Polarity = 1, Phase = 0,

receive edge of SPICLK

0.5P + 15

to SPICLK rising

Polarity = 1, Phase = 1,

0.5P + 15

to SPICLK falling

Polarity = 0, Phase = 0,

0.5P + 5

from SPICLK falling

Polarity = 0, Phase = 1,

0.5P + 5

Input Hold Time, SPIDI

from SPICLK rising

tih(SPC_SOMI)M

valid after

Polarity = 1, Phase = 0,

receive edge of SPICLK

0.5P + 5

from SPICLK rising

Polarity = 1, Phase = 1,

0.5P + 5

from SPICLK falling

(1)

P = SYSCLK3 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPIDO.

MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIDI.

(3)

The final data bit will be held on the SPIDO pin until the SPIDAT1 register is written with new data.

Peripheral Information and Electrical Specifications

125

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