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AT90PWM2 Datasheet(PDF) 293 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 293 Page - ATMEL Corporation |
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293 / 361 page  293 4317J–AVR–08/10 AT90PWM2/3/2B/3B Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 25.9 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 25-13 on page 284, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low 0 1 μs tWLRH WR Low to RDY/BSY High (1) 3.7 4.5 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase (2) 7.5 9 ms tXLOL XTAL1 Low to OE Low 0 ns tBVDV BS1 Valid to DATA valid 0 250 ns tOLDV OE Low to DATA Valid 250 ns tOHDZ OE High to DATA Tri-stated 250 ns Table 25-14. Parallel Programming Characteristics, V CC = 5V ± 10% (Continued) Symbol Parameter Min Typ Max Units |
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