AT90PWM3 datasheet(179/361 Pages) ATMEL

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179

4317J–AVR–08/10

AT90PWM2/3/2B/3B

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is sum-

marized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL

functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

Read/Write

R/W

Initial Value

00000000

Table 17-2.

CPOL Functionality

CPOL

Leading Edge

Trailing Edge

Rising

Falling

Rising

Table 17-3.

CPHA Functionality

CPHA

Leading Edge

Trailing Edge

Sample

Setup

Sample

AT90PWM3 Datasheet(PDF) 179 Page - ATMEL Corporation

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