Electronic Components Datasheet Search
  English  ▼

X  

118 Datasheet(PDF) 113 Page - Renesas Technology Corp

Part # 118
Description  RENESAS MCU
PDF  126 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

118 Datasheet(HTML) 113 Page - Renesas Technology Corp

Back Button 118 Datasheet HTML 109Page - Renesas Technology Corp 118 Datasheet HTML 110Page - Renesas Technology Corp 118 Datasheet HTML 111Page - Renesas Technology Corp 118 Datasheet HTML 112Page - Renesas Technology Corp 118 Datasheet HTML 113Page - Renesas Technology Corp 118 Datasheet HTML 114Page - Renesas Technology Corp 118 Datasheet HTML 115Page - Renesas Technology Corp 118 Datasheet HTML 116Page - Renesas Technology Corp 118 Datasheet HTML 117Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 113 / 126 page
background image
REJ03B0255-0110
Rev.1.10
Page 113 of 123
Jun 23, 2010
R32C/118 Group
5. Electrical Characteristics
VCC =3.3 V
Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta =Topr, unless otherwise noted)
Table 5.56
Serial Interface
Symbol
Characteristic
Value
Unit
Min.
Max.
tc(CK)
CLKi input clock period
200
ns
tw(CKH)
CLKi input high level pulse width
80
ns
tw(CKL)
CLKi input low level pulse width
80
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
Table 5.57
A/D Trigger Input
Symbol
Characteristic
Value
Unit
Min.
Max.
tw(ADH)
ADTRG input high level pulse width
Hardware trigger input high level pulse width
ns
tw(ADL)
ADTRG input low level pulse width
Hardware trigger input high level pulse width
125
ns
Table 5.58
External Interrupt INTi Input
Symbol
Characteristic
Value
Unit
Min.
Max.
tw(INH)
INTi input high level pulse width
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
tw(INL)
INTi input low level pulse width
Edge sensitive
250
ns
Level sensitive
tc(CPU) + 200
ns
Table 5.59
Intelligent I/O
Symbol
Characteristic
Value
Unit
Min.
Max.
tc(ISCLK2)
ISCLK2 input clock period
600
ns
tw(ISCLK2H)
ISCLK2 input high level pulse width
270
ns
tw(ISCLK2L)
ISCLK2 input low level pulse width
270
ns
tsu(RXD-ISCLK2) ISRXD2 input setup time
150
ns
th(ISCLK2-RXD) ISRXD2 input hold time
100
ns
3
φ
AD
----------



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com