16F1829 datasheet(171/420 Pages) MICROCHIP

171 / 420 page

 2010 Microchip Technology Inc.

Preliminary

DS41440A-page 171

PIC16F/LF1825/1829

18.0 SR LATCH

The module consists of a single SR Latch with multiple

Set and Reset inputs as well as separate latch outputs.

The SR Latch module includes the following features:

• Programmable input selection

• SR Latch output is available externally

• Separate Q and Q outputs

• Firmware Set and Reset

The SR Latch can be used in a variety of analog appli-

cations, including oscillator circuits, one-shot circuit,

hysteretic controllers, and analog timing applications.

18.1

Latch Operation

The latch is a Set-Reset Latch that does not depend on

a clock source. Each of the Set and Reset inputs are

active-high. The latch can be Set or Reset by:

• Software control (SRPS and SRPR bits)

• Comparator C1 output (SYNCC1OUT)

• Comparator C2 output (SYNCC2OUT)

(PIC16F/LF1829 only)

•SRI pin

• Programmable clock (SRCLK)

The SRPS and the SRPR bits of the SRCON0 register

may be used to Set or Reset the SR Latch, respec-

tively. The latch is Reset-dominant. Therefore, if both

Set and Reset inputs are high, the latch will go to the

Reset state. Both the SRPS and SRPR bits are self

resetting which means that a single write to either of the

bits is all that is necessary to complete a latch Set or

Reset operation.

The output from Comparator C1 or C2 can be used as

the Set or Reset inputs of the SR Latch. The output of

either Comparator can be synchronized to the Timer1

clock

source.

See

Section 19.0

“Comparator

Module” and Section 21.0 “Timer1 Module with

Gate Control” for more information.

An external source on the SRI pin can be used as the

Set or Reset inputs of the SR Latch.

An internal clock source is available that can periodically

Set or Reset the SR Latch. The SRCLK<2:0> bits in the

SRCON0 register are used to select the clock source

period. The SRSCKE and SRRCKE bits of the SRCON1

Latch, respectively.

18.2

Latch Output

The SRQEN and SRNQEN bits of the SRCON0 regis-

ter control the Q and Q latch outputs. Both of the SR

Latch outputs may be directly output to an I/O pin at the

same time.

The applicable TRIS bit of the corresponding port must

be cleared to enable the port pin output driver.

18.3

Effects of a Reset

Upon any device Reset, the SR Latch output is not ini-

tialized to a known state. The user’s firmware is

responsible for initializing the latch output before

enabling the output pins.

Note:

Enabling both the Set and Reset inputs

from any one source at the same time

may result in indeterminate operation, as

the Reset dominance cannot be assured.

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