MPC8378E datasheet(113/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

113

Clocking

22.2

Core PLL Configuration

RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the

e300 core clock (core_clk). Table 75 shows the encodings for RCWLR[COREPLL]. COREPLL values

that are not listed in Table 75 should be considered as reserved.

NOTE

Core VCO frequency = core frequency

× VCO divider

VCO divider has to be set properly so that the core VCO frequency is in the

range of 800–1600 MHz.

CFG_CLKIN_DIV doubles csb_clk if set high.

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 75. e300 Core PLL Configuration

RCWLR[COREPLL]

core_clk : csb_clk Ratio

VCO Divider 1

0–1

2–5

0000

PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core

directly)

nnnn

nn/a

n/a

0001

01:1

0001

01:1

0001

01:1

0001

1.5:1

0001

1.5:1

0001

1.5:1

0010

02:1

0010

02:1

0010

02:1

0010

2.5:1

0010

2.5:1

0010

2.5:1

0011

03:1

0011

03:1

0011

03:1

0011

3.5:1

0011

3.5:1

0011

3.5:1

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