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MPC8378E Datasheet(PDF) 125 Page - Freescale Semiconductor, Inc

Part # MPC8378E
Description  PowerQUICC II Pro Processor Hardware Specifications
PDF  127 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8378E Datasheet(HTML) 125 Page - Freescale Semiconductor, Inc

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
125
Document Revision History
26 Document Revision History
Table 83 provides a revision history for this hardware specification.
Table 83. Document Revision History
Revision
Date
Substantive Change(s)
4
11/2010
• In Table 25, “RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.
•In Table 45, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for tLBKHLR.
•In Section 10.2, “Local Bus AC Electrical Specifications,” and in Section 22, “Clocking,” updated LCCR
to LCRR.
•In Table 68, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and
TEST_SEL1 pins—no change in functionality.
3
03/2010
• Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.”
•In Table 39, “USB DC Electrical Characteristics,” and Table 40, “USB General Timing Parameters (ULPI
Mode Only),” added table footnotes .
•In Table 44, “Local Bus General Timing Parameters—PLL Enable Mode,” and Table 45, “Local Bus
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3.
•In Figure 26, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and
Figure 28, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
•In Figure 66, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added
heat spreader.
•In Section 24.6, “Pull-Up Resistor Requirements,” removed “Ethernet Management MDIO pin” from list
of open drain type pins.
•In Table 68, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
AVDD_P pins.
•in Table 68, “TePBGA II Pinout Listing,” added Note 17 to eTSEC pins.
•In Table 73, “CSB Frequency Options for Host Mode,” and Table 74, “CSB Frequency Options for Agent
Mode,” updated csb_clk frequencies available.
•In Table 80, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”



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