HT66F40 datasheet(129/244 Pages) HOLTEK

129 / 244 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev. 1.60

129

October 24, 2011

Counter Value

CCRP

CCRA

TnON

TnPAU

TnAPOL

CCRA Int.

Flag TnAF

CCRB Int.

Flag TnBF

TPnA Pin

(TnAOC=1)

Time

Pause

Resume

Stop

Counter

Restart

TnCCLR = 0;

TnAM [1:0] = 10, TnBM [1:0] = 10;

TnPWM [1:0] = 11

Output Pin

Reset to Initial value

Output controlled by

Other pin-shared function

Output Inverts

when TnAPOL

is high

CCRB

CCRP Int.

Flag TnPF

TPnB Pin

(TnBOC=1)

TPnB Pin

(TnBOC=0)

Duty Cycle set by CCRA

Duty Cycle set by CCRB

PWM Period set by CCRP

ETM PWM Mode -- Centre Aligned

Note:

1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period

2. TnPWM [1:0] =11 therefore the PWM is centre aligned

3. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01

4. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty

5. CCRP will generate an interrupt request when the counter decrements to its zero value

HT66F40 Datasheet(PDF) 129 Page - Holtek Semiconductor Inc

HT66F40 Datasheet(HTML) 129 Page - Holtek Semiconductor Inc

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