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TPS92510

www.ti.com

SLUSAE4A – JANUARY 2012 – REVISED JUNE 2012

DETAILED DESCRIPTION (continued)

(5)

(6)

(7)

Fixed Frequency PWM Control

The TPS92510 uses an adjustable, fixed-frequency, peak current mode control. Each switching cycle an internal

oscillator initiates the turn-on of the MOSFET. The LED current flows through the sense resistor and develops

the feedback voltage on the VSENSE pin. The error amplifier output (COMP pin) is compared to the high-side

MOSFET current. When the MOSFET current reaches the level set by the COMP pin voltage the MOSFET is

turned off.

Slope Compensation

The TPS92510 adds a compensating ramp to the MOSFET current signal. The slope compensation prevents

sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range.

Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS92510 is adjustable over a wide range from approximately 100 kHz to 2500

kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor

to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use

Equation 8 or the curves in Figure 5 or Figure 6. To reduce the solution size one typically sets the switching

frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum

controllable on time should be considered. The minimum controllable on time is typically 135 ns and limits the

maximum operating input voltage.

XXX

(8)

(9)

Synchronization to an External System Clock (RT/CLK)

The RT/CLK pin can be used to synchronize the regulator to an external system clock by connecting a square

wave to the RT/CLK pin through the circuit network as shown in Figure 23. The square wave amplitude must

transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 ns and

an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of

the PH is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit default

frequency is set by connecting the resistor from the RT/CLK pin to ground should the synchronization signal turn

off. It is recommended to use a frequency set resistor connected as shown in Figure 23 through a 50-

Ω resistor

to ground.

The resistor should set the switching frequency close to the external CLK frequency. It is recommended to ac

couple the synchronization signal through a 470-pF ceramic capacitor to RT/CLK pin and a 4-k

Ω series resistor.

The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in

applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK

threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is

removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since

there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the

external resistor. The device transitions from the resistor mode to the PLL mode and then increases or

decreases the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.

Copyright © 2012, Texas Instruments Incorporated

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Product Folder Link(s): TPS92510