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PIC16F87 Datasheet(PDF) 189 Page - Microchip Technology |
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PIC16F87 Datasheet(HTML) 189 Page - Microchip Technology |
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189 / 230 page  2002-2013 Microchip Technology Inc. DS30487D-page 189 PIC16F87/88 FIGURE 18-18: A/D CONVERSION TIMING TABLE 18-14: A/D CONVERSION REQUIREMENTS 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA Sampling Stopped DONE NEW_DATA (TOSC/2)(1) 98 7 2 1 0 Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1 TCY Param No. Symbol Characteristic Min Typ† Max Units Conditions 130 TAD A/D Clock Period PIC16F87/88 1.6 — — sTOSC based, VREF 3.0V PIC16LF87/88 3.0 — — sTOSC based, VREF 2.0V PIC16F87/88 2.0 4.0 6.0 s A/D RC mode PIC16LF87/88 3.0 6.0 9.0 s A/D RC mode 131 TCNV Conversion Time (not including S/H time) (Note 1) —12 TAD 132 TACQ Acquisition Time (Note 2) 10* 40 — — — s s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 5.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D Clock Start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES registers may be read on the following TCY cycle. 2: See Section 12.1 “A/D Acquisition Requirements” for minimum conditions. |
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