M68ICS08GR datasheet(312/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

Technical Data

MC68HC908GR8 — Rev 4.0

312

Serial Peripheral Interface (SPI)

MOTOROLA

Figure 20-10. Clearing SPRF When OVRF Interrupt Is Not Enabled

20.8.2 Mode Fault Error

Setting the SPMSTR bit selects master mode and configures the

SPSCK and MOSI pins as outputs and the MISO pin as an input.

Clearing SPMSTR selects slave mode and configures the SPSCK and

MOSI pins as inputs and the MISO pin as an output. The mode fault bit,

MODF, becomes set any time the state of the slave select pin, SS, is

inconsistent with the mode selected by SPMSTR.

To prevent SPI pin contention and damage to the MCU, a mode fault

error occurs if:

•

The SS pin of a slave SPI goes high during a transmission

•

The SS pin of a master SPI goes low at any time

For the MODF flag to be set, the mode fault error enable bit (MODFEN)

must be set. Clearing the MODFEN bit does not clear the MODF flag but

does prevent MODF from being set again after MODF is cleared.

READ

OVRF

SPRF

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 1 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

CPU READS BYTE 1 IN SPDR,

CPU READS SPSCR AGAIN

BYTE 2 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.

CPU READS BYTE 2 IN SPDR,

CPU READS SPSCR AGAIN

CPU READS BYTE 2 SPDR,

BYTE 4 SETS SPRF BIT.

CPU READS SPSCR.

CPU READS BYTE 4 IN SPDR,

CPU READS SPSCR AGAIN

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

CLEARING OVRF BIT.

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

SPI RECEIVE

COMPLETE

AND OVRF BIT CLEAR.

SPSCR

SPDR

Freescale Semiconductor, Inc.

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