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ST72F521R6TA Datasheet(PDF) 90 Page - STMicroelectronics |
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ST72F521R6TA Datasheet(HTML) 90 Page - STMicroelectronics |
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90 / 215 page  ST72F521, ST72521B 90/215 SERIAL PERIPHERAL INTERFACE (Cont’d) –SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven by stand- ard I/O ports on the master MCU. 10.5.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 54. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the mas- ter. When the master device transmits data to a slave device via MOSI pin, the slave device re- sponds by sending data to the master device via the MISO pin. This implies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 57) but master and slave must be programmed with the same timing mode. Figure 54. Single Master/ Single Slave Application 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 8-BIT SHIFT REGISTER MISO MOSI MOSI MISO SCK SCK SLAVE MASTER SS SS +5V MSBit LSBit MSBit LSBit Not used if SS is managed by software |
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