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ST72F521R6TA Datasheet(PDF) 44 Page - STMicroelectronics |
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ST72F521R6TA Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 215 page  ST72F521, ST72521B 44/215 POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register). 8.4.1 ACTIVE-HALT MODE ACTIVE-HALT mode is the lowest power con- sumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ in- struction when the OIE bit of the Main Clock Con- troller Status register (MCCSR) is set (see section 10.2 on page 58 for more details on the MCCSR register). The MCU can exit ACTIVE-HALT mode on recep- tion of an MCC/RTC interrupt or a RESET. In ROM devices, external interrupts can be used to wake- up the MCU. When exiting ACTIVE-HALT mode by means of an interrupt, no 256 or 4096 CPU cy- cle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vec- tor which woke it up (see Figure 27). When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable in- terrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are run- ning to keep a wake-up time base. All other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). The safeguard against staying locked in ACTIVE- HALT mode is provided by the oscillator interrupt. Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. CAUTION: When exiting ACTIVE-HALT mode fol- lowing an MCC/RTC interrupt, OIE bit of MCCSR register must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU de- lay depending on option byte). Otherwise, the ST7 enters HALT mode for the remaining tDELAY peri- od. Figure 26. ACTIVE-HALT Timing Overview Figure 27. ACTIVE-HALT Mode Flow-chart Notes: 1. This delay occurs only if the MCU exits ACTIVE- HALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC reg- ister are set to the current software priority level of the interrupt routine and restored when the CC register is popped. 4. In flash devices only the MCC/RTC interrupt can exit the MCU from ACTIVE-HALT mode. MCCSR OIE bit Power Saving Mode entered when HALT instruction is executed 0 HALT mode 1 ACTIVE-HALT mode HALT RUN RUN 256 OR 4096 CPU CYCLE DELAY 1) RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR ACTIVE [MCCSR.OIE=1] HALT INSTRUCTION RESET Y N N Y CPU OSCILLATOR PERIPHERALS 2) I[1:0] BITS ON OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF XX 3) ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX 3) ON 256OR 4096CPU CLOCK CYCLE DELAY (MCCSR.OIE=1) INTERRUPT 4) |
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