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ST72F262G2B5 Datasheet(PDF) 60 Page - STMicroelectronics |
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ST72F262G2B5 Datasheet(HTML) 60 Page - STMicroelectronics |
60 / 172 page ![]() ST72260Gx, ST72262Gx, ST72264Gx 60/172 16-BIT TIMER (Cont’d) Figure 39. Input Capture Block Diagram Figure 40. Input Capture Timing Diagram Note: The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3 CPU clock cycles. This depends on the moment when the ICAP event happens relative to the timer clock. ICIE CC0 CC1 16-BIT FREE RUNNING COUNTER IEDG1 (Control Register 1) CR1 (Control Register 2) CR2 ICF2 ICF1 0 0 0 (Status Register) SR IEDG2 ICAP1 ICAP2 EDGE DETECT CIRCUIT2 16-BIT IC1R Register IC2R Register EDGE DETECT CIRCUIT1 pin pin FF01 FF02 FF03 FF03 TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The active edge is the rising edge. |
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