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ST72F262G2B5 Datasheet(PDF) 24 Page - STMicroelectronics

Part # ST72F262G2B5
Description  8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F262G2B5 Datasheet(HTML) 24 Page - STMicroelectronics

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)
The System Integrity Management block contains
group the Low voltage Detector (LVD) and Auxilia-
ry Voltage Detector (AVD) functions. It is managed
by the SICSR register.
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to Section 12.2.1 on page 123 for further de-
tails.
6.4.1 Low Voltage Detector (LVD)
The Low Voltage Detector function (LVD) gener-
ates a static reset when the VDD supply voltage is
below a VIT- reference value. This means that it
secures the power-up as well as the power-down
keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
VDD is below:
–VIT+ when VDD is rising
–VIT- when VDD is falling
The LVD function is illustrated in Figure 14.
The voltage threshold can be configured by option
byte to be low, medium or high.
Provided the minimum VDD value (guaranteed for
the oscillator frequency) is above VIT-, the MCU
can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
The LVD allows the device to be used without any
external RESET circuitry.
The LVD is an optional function which can be se-
lected by option byte.
Use of LVD with capacitive power supply: with this
type of power supply, if power cuts occur in the ap-
plication, it is recommended to pull VDD down to
0V to ensure optimum restart conditions. Refer to
circuit example in Figure 91 on page 151 and note
6.
It is recommended to make sure that the VDD sup-
ply voltage rises monotonously when the device is
exiting from Reset, to ensure the application func-
tions properly.
Figure 14. Low Voltage Detector vs Reset
VDD
VIT+
RESET
VIT-
Vhys


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