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EP3SL150 Datasheet(PDF) 106 Page - Altera Corporation

Part # EP3SL150
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL150 Datasheet(HTML) 106 Page - Altera Corporation

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1–96
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Table 1–62 lists the EP3SL110 row pins input timing parameters for single-ended I/O
standards.
Table 1–62. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.910
-0.883
-1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881
ns
t
h
1.025
1.015
1.440
1.648
1.792
1.822
2.066
1.682
1.794
1.831
2.104
ns
GCLK
PLL
t
su
0.992
1.013
1.646
1.862
1.976
1.860
1.804
1.870
1.998
1.880
1.856
ns
t
h
-0.741
-0.746
-1.246 -1.412 -1.475 -1.388 -1.322 -1.411 -1.486 -1.398 -1.371
ns
3.3-V
LVCMOS
GCLK
t
su
-0.910
-0.883
-1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881
ns
t
h
1.025
1.015
1.440
1.648
1.792
1.822
2.066
1.682
1.794
1.831
2.104
ns
GCLK
PLL
t
su
0.992
1.013
1.646
1.862
1.976
1.860
1.804
1.870
1.998
1.880
1.856
ns
t
h
-0.741
-0.746
-1.246 -1.412 -1.475 -1.388 -1.322 -1.411 -1.486 -1.398 -1.371
ns
3.0-V LVTTL
GCLK
t
su
-0.916
-0.894
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
ns
t
h
1.031
1.026
1.437
1.649
1.795
1.825
2.069
1.681
1.799
1.836
2.109
ns
GCLK
PLL
t
su
0.986
1.002
1.649
1.861
1.973
1.857
1.801
1.871
1.993
1.875
1.851
ns
t
h
-0.735
-0.735
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
ns
3.0-V
LVCMOS
GCLK
t
su
-0.916
-0.894
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
ns
t
h
1.031
1.026
1.437
1.649
1.795
1.825
2.069
1.681
1.799
1.836
2.109
ns
GCLK
PLL
t
su
0.986
1.002
1.649
1.861
1.973
1.857
1.801
1.871
1.993
1.875
1.851
ns
t
h
-0.735
-0.735
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
ns
2.5 V
GCLK
t
su
-0.904
-0.887
-1.258 -1.455 -1.577 -1.622 -1.861 -1.473 -1.566 -1.620 -1.896
ns
t
h
1.019
1.019
1.446
1.662
1.810
1.840
2.084
1.690
1.809
1.846
2.119
ns
GCLK
PLL
t
su
0.998
1.009
1.640
1.848
1.958
1.842
1.786
1.862
1.983
1.865
1.841
ns
t
h
-0.747
-0.742
-1.240 -1.398 -1.457 -1.370 -1.304 -1.403 -1.471 -1.383 -1.356
ns
1.8 V
GCLK
t
su
-0.873
-0.918
-1.298 -1.402 -1.575 -1.530 -1.859 -1.402 -1.567 -1.526 -1.897
ns
t
h
0.990
1.051
1.486
1.612
1.808
1.751
2.082
1.622
1.810
1.756
2.120
ns
GCLK
PLL
t
su
0.968
0.977
1.600
1.815
1.960
1.844
1.788
1.829
1.982
1.864
1.840
ns
t
h
-0.716
-0.709
-1.200 -1.365 -1.459 -1.372 -1.306 -1.370 -1.470 -1.382 -1.355
ns
1.5 V
GCLK
t
su
-0.863
-0.907
-1.274 -1.370 -1.507 -1.462 -1.791 -1.371 -1.502 -1.461 -1.832
ns
t
h
0.980
1.040
1.462
1.580
1.740
1.683
2.014
1.591
1.745
1.691
2.055
ns
GCLK
PLL
t
su
0.978
0.988
1.624
1.847
2.028
1.912
1.856
1.860
2.047
1.929
1.905
ns
t
h
-0.726
-0.720
-1.224 -1.397 -1.527 -1.440 -1.374 -1.401 -1.535 -1.447 -1.420
ns
1.2 V
GCLK
t
su
-0.803
-0.854
-1.195 -1.269 -1.348 -1.303 -1.632 -1.275 -1.347 -1.306 -1.677
ns
t
h
0.920
0.987
1.383
1.479
1.581
1.524
1.855
1.495
1.590
1.536
1.900
ns
GCLK
PLL
t
su
1.038
1.041
1.703
1.948
2.187
2.071
2.015
1.956
2.202
2.084
2.060
ns
t
h
-0.786
-0.773
-1.303 -1.498 -1.686 -1.599 -1.533 -1.497 -1.690 -1.602 -1.575
ns



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