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EP3SL150 Datasheet(PDF) 161 Page - Altera Corporation

Part # EP3SL150
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SL150 Datasheet(HTML) 161 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–151
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
1.5-V HSTL
CLASS I
GCLK
t
su
1.010
1.025
-1.969 -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475
ns
t
h
1.338
1.384
1.674
-1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463
ns
GCLK
PLL
t
su
-1.304
-1.332
2.207
2.117
2.381
2.289
2.713
2.244
2.418
2.289
2.713
ns
t
h
1.438
1.484
-1.969
1.902
2.208
2.098
2.007
1.889
2.113
2.098
2.007
ns
1.5-V HSTL
CLASS II
GCLK
t
su
0.909
0.927
1.674
-1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475
ns
t
h
-0.632
-0.632
2.207
-1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463
ns
GCLK
PLL
t
su
-1.304
-1.332
2.207
2.117
2.381
2.289
2.713
2.244
2.418
2.289
2.713
ns
t
h
1.438
1.484
2.207
1.902
2.208
2.098
2.007
1.889
2.113
2.098
2.007
ns
1.2-V HSTL
CLASS I
GCLK
t
su
0.909
0.927
2.207
-1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475
ns
th
-0.632
-0.632
2.207
-1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463
ns
GCLK
PLL
t
su
-1.298
-1.321
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
ns
t
h
1.432
1.473
1.671
1.862
1.969
1.850
1.775
1.751
1.869
1.850
1.775
ns
1.2-V HSTL
CLASS II
GCLK
tsu
0.915
0.938
2.210
2.223
2.633
2.541
2.966
2.384
2.665
2.541
2.966
ns
t
h
-0.638
-0.643
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
ns
GCLK
PLL
tsu
-1.298
-1.321
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
ns
t
h
1.432
1.473
1.671
1.862
1.969
1.850
1.775
1.751
1.869
1.850
1.775
ns
3.0-V PCI
GCLK
t
su
0.915
0.938
2.210
2.223
2.633
2.541
2.966
2.384
2.665
2.541
2.966
ns
t
h
-0.638
-0.643
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
ns
GCLK
PLL
t
su
-1.304
-1.332
2.207
2.224
2.636
2.544
2.969
2.383
2.670
2.544
2.969
ns
th
1.438
1.484
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
ns
3.0-V
PCI-X
GCLK
t
su
0.909
0.927
1.674
1.861
1.966
1.847
1.772
1.752
1.864
1.847
1.772
ns
th
-0.632
-0.632
2.207
2.224
2.636
2.544
2.969
2.383
2.670
2.544
2.969
ns
GCLK
PLL
t
su
-1.304
-1.332
2.216
2.237
2.651
2.559
2.984
2.392
2.680
2.559
2.984
ns
t
h
1.438
1.484
-1.978 -1.992 -2.386 -2.309 -2.730 -2.140 -2.403 -2.309 -2.730
ns
Table 1–82. EP3SL200 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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