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ADNS-5095 Datasheet(PDF) 9 Page - AVAGO TECHNOLOGIES LIMITED |
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ADNS-5095 Datasheet(HTML) 9 Page - AVAGO TECHNOLOGIES LIMITED |
9 / 31 page ![]() 9 Table 3. AC Electrical Specifications Electrical characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 2.8 V. Parameter Symbol Min. Typ. Max. Units Notes Motion Delay after Reset tMOT-RST 50 ms From RESET register write to valid motion Forced Rest Enable tREST-EN 1 s From Rest Mode(RM) bits set to target rest mode Wake from Forced Rest tREST-DIS 1 s From Rest Mode(RM) bits cleared to valid motion Power Down tPD 50 ms From PD active (when bit 1 of register 0x0d is set) to low current Wake from Power Down tWAKEUP 50 55 ms From PD inactive (when write 0x5a to regis- ter 0x3a) to valid motion MISO Rise Time tr-MISO 40 200 ns CL = 100 pF MISO Fall Time tf-MISO 40 200 ns CL = 100 pF MISO Delay after SCLK tDLY-MISO 120 ns From SCLK falling edge to MISO data valid, no load conditions MISO Hold Time thold-MISO 500 1/fSCLK ns Data held until next falling SCLK edge MOSI Hold Time thold-MOSI 200 ns Amount of time data is valid after SCLK rising edge MOSI Setup Time tsetup-MOSI 120 ns From data valid to SCLK rising edge SPI Time between Write Commands tSWW 30 μs From rising SCLK for last bit of the first data byte, Commands to rising SCLK for last bit of the second data byte SPI Time between Write and Read Com- mands tSWR 20 μs From rising SCLK f or last bit of the first data byte, to rising SCLK for last bit of the second address byte SPI Time between Read and Subsequent Commands tSRW tSRR 250 ns From rising SCLK for last bit of the first data byte, to falling SCLK for the first bit of the next address SPI Read Address-Data Delay tSRAD 4 μs From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read NCS Inactive after Mo- tion Burst tBEXIT 250 ns Minimum NCS inactive time after motion burst before next SPI usage NCS to SCLK Active tNCS-SCLK 120 ns From NCS falling edge to first SCLK falling edge SCLK to NCS Inactive (for Read Operation) tSCLK-NCS 120 ns From last SCLK rising edge to NCS rising edge, for valid MISO data transfer SCLK to NCS Inactive (for Write Operation) tSCLK-NCS 20 μs From last SCLK rising edge to NCS rising edge, for valid MOSI data transfer NCS to MISO high-Z tNCS-MISO 250 ns From NCS rising edge to MISO high-Z state Transient Supply Current IDDT 60 mA Max supply current during a VDD ramp from 0 to VDD |
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