32GA002 datasheet(139/268 Pages) MICROCHIP

139 / 268 page

 2010 Microchip Technology Inc.

DS39881D-page 139

PIC24FJ64GA004 FAMILY

14.4

Output Compare Register

OCxCON: OUTPUT COMPARE x CONTROL REGISTER

U-0

R/W-0

U-0

—

—OCSIDL

—

bit 15

bit 8

U-0

R-0, HC

R/W-0

—

OCFLT

OCTSEL

OCM2(1)

OCM1(1)

OCM0(1)

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-14

Unimplemented:

Read as ‘0’

bit 13

OCSIDL:

Stop Output Compare x in Idle Mode Control bit

= Output Compare x will halt in CPU Idle mode

= Output Compare x will continue to operate in CPU Idle mode

bit 12-5

Unimplemented:

Read as ‘0’

bit 4

OCFLT:

PWM Fault Condition Status bit

= PWM Fault condition has occurred (cleared in HW only)

= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)

bit 3

OCTSEL:

Output Compare x Timer Select bit

= Timer3 is the clock source for Output Compare x

= Timer2 is the clock source for Output Compare x

Refer to the device data sheet for specific time bases available to the output compare module.

bit 2-0

OCM2:OCM0:

Output Compare x Mode Select bits(1)

111

= PWM mode on OCx, Fault pin, OCFx, enabled(2)

110

= PWM mode on OCx, Fault pin, OCFx, disabled(2)

101

= Initialize OCx pin low, generate continuous output pulses on OCx pin

100

= Initialize OCx pin low, generate single output pulse on OCx pin

011

= Compare event toggles OCx pin

010

= Initialize OCx pin high, compare event forces OCx pin low

001

= Initialize OCx pin low, compare event forces OCx pin high

000

= Output compare channel is disabled

Note 1:

RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select”

OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.

32GA002 Datasheet(PDF) 139 Page - Microchip Technology

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