48GA004 datasheet(143/268 Pages) MICROCHIP

143 / 268 page

 2010 Microchip Technology Inc.

DS39881D-page 143

PIC24FJ64GA004 FAMILY

To set up the SPI module for the Enhanced Buffer

Master mode of operation:

If using interrupts:

Clear the SPIxIF bit in the respective IFSx

Set the SPIxIE bit in the respective IECx

Write the SPIxIP bits in the respective IPCx

Write the desired settings to the SPIxCON1 and

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 1.

Clear the SPIROV bit (SPIxSTAT<6>).

Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

Write the data to be transmitted to the SPIxBUF

as soon as data is written to the SPIxBUF

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

Clear the SPIxBUF register.

If using interrupts:

• Clear the SPIxIF bit in the respective IFSx

• Set the SPIxIE bit in the respective IECx

• Write the SPIxIP bits in the respective IPCx

Write the desired settings to the SPIxCON1 and

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 0.

Clear the SMP bit.

If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

Clear the SPIROV bit (SPIxSTAT<6>).

Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-2:

SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

Internal Data Bus

SDIx

SDOx

SSx/FSYNCx

SCKx

SPIxSR

bit0

Shift Control

Edge

Select

FCY

Primary

1:1/4/16/64

Enable

Prescaler

Secondary

Prescaler

1:1 to 1:8

Sync

Clock

Control

SPIxBUF

Control

Transfer

Write SPIxBUF

Read SPIxBUF

SPIxCON1<1:0>

SPIxCON1<4:2>

Master Clock

8-Level FIFO

Transmit Buffer

8-Level FIFO

Receive Buffer

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