 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
18F8680 Datasheet(PDF) 249 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
18F8680 Datasheet(HTML) 249 Page - Microchip Technology |
|
|
249 / 496 page  2004 Microchip Technology Inc. DS30491C-page 247 PIC18F6585/8585/6680/8680 18.4 USART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is sup- plied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) The first word will immediately transfer to the TSR register and transmit. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. e) If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. To set up a synchronous slave transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. 2. Clear bits CREN and SREN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 8. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x TXREG USART Transmit Register 0000 0000 0000 0000 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 BAUDCON — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
