18F8680 datasheet(138/496 Pages) MICROCHIP

138 / 496 page

PIC18F6585/8585/6680/8680

DS30491C-page 136

 2004 Microchip Technology Inc.

10.5

PORTE, TRISE and LATE

Registers

PORTE is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISE bit (= 0)

will make the corresponding PORTE pin an output (i.e.,

put the contents of the output latch on the selected pin).

Read-modify-write operations on the LATE register

read and write the latched output value for PORTE.

PORTE is an 8-bit port with Schmitt Trigger input

buffers. Each pin is individually configurable as an input

or output. PORTE is multiplexed with the Enhanced

CCP module (Table 10-9).

On PIC18F8X8X devices, PORTE is also multiplexed

with the system bus as the external memory interface;

the I/O bus is available only when the system bus is

disabled by setting the EBDIS bit in the MEMCON

Microprocessor or Extended Microcontroller mode, then

the PORTE<7:0> becomes the high byte of the address/

data bus for the external program memory interface. In

Microcontroller mode, the PORTE<2:0> pins become the

control inputs for the Parallel Slave Port when bit

PSPMODE

(PSPCON<4>)

set.

(Refer

Section 4.1.1

“PIC18F8X8X

Program

Memory

Modes” for more information on program memory

modes.)

When the Parallel Slave Port is active, three PORTE

pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)

function as its control inputs. This automatically occurs

when the PSPMODE bit (PSPCON<4>) is set. Users

must also make certain that bits TRISE<2:0> are set to

configure the pins as digital inputs and the ADCON1

control functions are summarized in Table 10-9.

Pin RE7 can be configured as the alternate peripheral

pin for the CCP2 module when the device is operating

in Microcontroller mode. This is done by clearing the

configuration bit, CCP2MX, in configuration register,

CONFIG3H (CONFIG3H<0>).

EXAMPLE 10-5:

INITIALIZING PORTE

Note:

For PIC18F8X8X (80-pin) devices operat-

ing in other than Microcontroller mode,

PORTE defaults to the system bus on

Power-on Reset.

CLRF

PORTE

; Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

03h

; Value used to

; initialize data

; direction

MOVWF

TRISE

; Set RE1:RE0 as inputs

; RE7:RE2 as outputs

18F8680 Datasheet(PDF) 138 Page - Microchip Technology

18F8680 Datasheet(HTML) 138 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL