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AM79C970A Datasheet(PDF) 130 Page - Advanced Micro Devices |
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AM79C970A Datasheet(HTML) 130 Page - Advanced Micro Devices |
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130 / 219 page  AMD P R E L I M I N A R Y 130 Am79C970A CSR40: Current Receive Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZEROs. 11–0 CRBC Current Receive Byte Count. This field is a copy of the BCNT field of RMD1 of the current receive descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR41: Current Receive Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 CRST Current Receive Status. This field is a copy of bits 31–16 of RMD1 of the current receive descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR42: Current Transmit Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZEROs. 11–0 CXBC Current Transmit Byte Count. This field is a copy of the BCNT field of TMD1 of the current transmit descriptor. 15–0 CXST Current Transmit Status. This field is a copy of bits 31–16 of TMD1 of the current transmit descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR44: Next Receive Byte Count Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–12 RES Reserved locations. Read and written as ZEROs. 11–0 NRBC Next Receive Byte Count. This field is a copy of the BCNT field of RMD1 of the next receive descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR45: Next Receive Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NRST Next Receive Status. This field is a copy of bits 31–16 of RMD1 of the next receive descriptor. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. CSR46: Poll Time Counter Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 POLL Poll Time Counter. This counter is incremented by the PCnet-PCI II controller microcode and is used to trigger the descriptor ring polling operation of the PCnet-PCI II controller. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET or by setting the STOP bit. |
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