| Electronic Components Datasheet Search |
|
PIC18F242 Datasheet(PDF) 290 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F242 Datasheet(HTML) 290 Page - Microchip Technology |
|
290 / 332 page ![]() PIC18FXX2 DS39564C-page 288 © 2006 Microchip Technology Inc. TABLE 22-22: A/D CONVERSION REQUIREMENTS Param No. Symbol Characteristic Min Max Units Conditions 130 TAD A/D clock period PIC18FXXX 1.6 20(4) μsTOSC based PIC18FXXX 2.0 6.0 μs A/D RC mode 131 TCNV Conversion time (not including acquisition time) (Note 1) 11 12 TAD 132 TACQ Acquisition time (Note 2) 5 10 — — μs μs VREF = VDD = 5.0V VREF = VDD = 2.5V 135 TSWC Switching Time from convert → sample — (Note 3) Note 1: ADRES register may be read on the following TCY cycle. 2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not changed by more than 1 LSB from the last sampled voltage. The source impedance ( RS) on the input channels is 50 Ω. See Section 17.0 for more information on acquisition time consideration. 3: On the next Q4 cycle of the device clock. 4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |