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UPD17708 Datasheet(PDF) 251 Page - NEC |
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UPD17708 Datasheet(HTML) 251 Page - NEC |
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251 / 356 page  251 µPD17704, 17705, 17707, 17708, 17709 <2> If forced wait is set in wait status Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (3/4) <4> If wait status is released when it has been already released The clock output waveform is not affected. The clock counter is not reset. Shif clock Wait period Wait period Forced wait set by SIO1TS <3> If forced wait is set after wait status has been released Note that the clock counter is reset. Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (4/4) a b Wait status Wait released status 1/fSC Shift clock Shift clock Forced wait by SIO1TS Wait released a b Wait status Wait released status 1/fSC a + b = 1/2fSC a + b = 1/2fSC Forced wait by SIO1TS Wait released |
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