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UPD17708 Datasheet(PDF) 290 Page - NEC |
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UPD17708 Datasheet(HTML) 290 Page - NEC |
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290 / 356 page  290 µPD17704, 17705, 17707, 17708, 17709 19.3 Clock Selection Block and Clock Generation Block The clock selection block selects the output frequency of BEEP1 and BEEP0 by using the BEEP clock selection register. The clock generation block generates the clock to be output to BEEP0 and BEEP1. The clock frequency generated is 1 kHz, 3 kHz, 4 kHz, 6.7 kHz, 67 Hz, or 200 Hz. Figure 19-4. Configuration of BEEP Clock Selection Register Name Flag symbol b3 B E E P 1 C K 1 b2 B E E P 1 C K 0 b1 B E E P 0 C K 1 b0 B E E P 0 C K 0 Address 14H Read/Write R/W BEEP clock selection Power-ON reset WDT&SP reset CE reset Clock stop 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 kHz 3 kHz 4 kHz 6.7 kHz Sets output frequency of BEEP0 4 kHz 3 kHz 200 Hz 67 Hz Sets output frequency of BEEP1 0 0 1 1 0 1 0 1 0 0 1 1 |
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