UPD17708 datasheet(226/356 Pages) NEC

226 / 356 page

226

µPD17704, 17705, 17707, 17708, 17709

Figure 16-7. Configuration of Serial I/O0 Wait Control Register

Name

Flag symbol

Address

0EH

Read/Write

R/W

Serial I/O0 wait control

Power-ON reset

WDT&SP reset

CE reset

Clock stop

No wait

Data wait

Acknowledge

wait

Address wait

Does not wait

Sets wait condition

I2C bus mode

Name

Serial I/O mode

Waits at falling edge of shift

clocks when value of clock

counter is “8”

Waits at falling edge of shift

clock when value of clock

counter is “9”

Waits at falling edge of clock

when value of clock counter

is “8” after detection of start

condition

Wait at rising edge of shift

clock when value of clock

counter is “8”

Setting prohibited

Forced wait

Releases wait status

(serial communication starts)

Sets wait and detects wait status

When flag is written

When flag is read

Waits under condition of SIO0WRQ0

and 1 flags

Serial communication in progress

Reception

(SIO0TX = 0)

Transmission

(SIO0TX = 1)

Sets and detects acknowledge signal in I2C bus mode

I2C bus mode

Serial I/O mode

Retains “0”

Detects acknowledge

of slave (acknowledge

is “0” )

Detects acknowledge

of slave (acknowledge

is “1” )

Outputs “0” as

acknowledge

Outputs “1” as

acknowledge

UPD17708 Datasheet(PDF) 226 Page - NEC

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