Data Sheet S11822EJ4V0DS00

9

1. PIN FUNCTIONS

1.1 PMD Interface

(1/2)

Pin name

Pin No.

I/O level

I/O

Function

RDIT

54

P-ECL

True(+)

I

RDIC

55

P-ECL

Complement(-)

I

Serial receive data input. When PSEL [1:0] is set to 00, the data is

sampled on a clock recovered by the internal clock recovery PLL.

When PSEL [1:0] is set to 01, the data is sampled on the clock input

to RCIT/RCIC.

RCIT

51

P-ECL

True(+)

I

RCIC

52

P-ECL

Complement(-)

I

Serial receive clock input (155.52 MHz).

When PSEL [1:0] is set to 01, the input is used as a receive clock.

TDOT

47

P-ECL

True(+)

O

TDOC

48

P-ECL

Complement(-)

O

Serial transmit data output. The data is output in sync with the rising

edge of the serial clock TCOT.

TCOT

43

P-ECL

True(+)

O

TCOC

44

P-ECL

Complement(-)

O

Serial transmit clock output (155.52 MHz).

When PSEL [1:0] is set to 00, the clock generated by the internal

synthesizer PLL is output as the transmit clock. When PSEL [1:0] is

set to 01, the clock supplied to TFKT/TFKC is output.

Depending on the mode selected, the transmit data may be latched

by the receive clock for output. Even in such a case, this pin outputs

the clock of the internal synthesizer or the clock input to the

TFKT/TFKC pin in accordance with the setting of the PSEL[1:0] pins.

It does not output the receive recovery clock.

TFKT

40

P-ECL

True(+)

I

TFKC

41

P-ECL

Complement(-)

I

Serial transmit clock input (155.52 MHz).

When PSEL [1:0] is set to 01, the input is used as the transmit clock.

RPD0-

RPD7

61-68

TTL*

I

Parallel receive data input. When PSEL [1:0] is set to 1X, these pins

input receive data. The data is sampled in sync with the rising edge

of parallel receive clock RPC.

RPC

59

TTL*

I

Parallel receive clock input (19.44 MHz).

When PSEL [1:0] is set to 1X to select parallel mode, this pin inputs a

19.44 MHz receive clock.

TPD0-

TPD7

17-24

TTL*

O

Parallel transmit data output. When PSEL [1:0] is set to 1X to select

parallel mode, these pins output transmit data in sync with the rising

edge of PC.

TPC

25

TTL*

O

Parallel transmit clock output. When PSEL [1:0] is set to 1X, this pin

outputs the clock (19.44 MHz) supplied to TFC.