6

TC811

© 2001 Microchip Technology Inc.

DS21472A

3-1/2 Digit Analog-To-Digital Converter with

Hold and Differential Reference Inputs

TC811-7 11/5/96

Accuracy in a dual slope converter is unrelated to the

integrating resistor and capacitor values as long as they are

stable during a measurement cycle. An inherent benefit of

the dual slope technique is noise immunity. Noise spikes are

integrated or averaged to zero during the integration peri-

ods, making integration ADCs immune to the large conver-

sion errors that plague successive approximation convert-

ers in high noise environments. Interfering signals, with

frequency components at multiples of the averaging (inte-

grating) period, will be attenuated. (see Figure 3). Integrat-

ing ADCs commonly operate with the signal integration

period set to a multiple of the 50/60Hz power line period.

THEORY OF OPERATION

Analog Section

In addition to the basic integrate and deintegrate dual-

slope cycles discussed above, the TC811 design incorpo-

rates an “Integrator Output Zero” cycle and an “Auto Zero”

cycle. These additional cycles ensure the integrator starts at

0V (even after a severe overrange conversion) and that all

offset voltage errors (buffer amplifier, integrator and com-

parator) are removed from the conversion. A true digital zero

reading is assured without any external adjustments.

A complete conversion consists of four distinct phases:

(1) Integrator Output Zero Cycle

(2) Auto Zero Cycle

(3) Signal Integrate Cycle

(4) Reference Deintegrate Cycle

Figure 4a. Conversion Timing During Normal Operation

Figure 4b. Conversion Timing During Overrange Operation

is typically 10 to 15

µV.

The Auto Zero duration is from 910 to 2,900 counts for

non-over-range conversions and from 300 to 910 counts for

overrange conversions.

Signal Integration Cycle

Upon completion of the Auto Zero cycle, the Auto Zero

loop is opened and the internal differential inputs connect to

for a fixed time period which, in the TC811 is 1000 counts

(4000 clock periods). The externally set clock frequency is

divided by four before clocking the internal counters. The

integration time period is:

The differential input voltage must be within the device

common-mode range when the converter and measured

system share the same power supply common (ground).

If the converter and measured system do not share the same

power supply common, as in battery powered applications,

Integrator Output Zero Cycle

This phase guarantees that the integrator output is at

zero volts before the system zero phase is entered, ensuring

that the true system offset voltages will be compensated for

even after an overrange conversion. The duration of this

phase is variable, being a function of the number of counts

(clock cycles) required for deintegration.

The Integrator Output Zero cycle will last from 11 to 140

counts for non-over-range conversions and from 31 to 640

counts for overrange conversions.

Auto Zero Cycle

During the Auto Zero cycle, the differential input signal

is disconnected from the measurement circuit by opening

internal analog switches and the internal nodes are shorted

to Analog Common (0V ref.) to establish a zero input

condition. Additional analog switches close a feedback loop

around the integrator and comparator to permit comparator

offset voltage error compensation. A voltage established on

during the measurement cycle. The Auto Zero cycle residual

4000

INT

DE-INT

ZI

AZ

4000

910–2900

1–2000

1000

11–140

AZ

4000

ZI

DE-INT

INT

1000

2001–2090

31–640

300–910