![]() |
Electronic Components Datasheet Search |
|
NCL30161 Datasheet(PDF) 6 Page - ON Semiconductor |
|
|
NCL30161 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 8 page ![]() NCL30161 http://onsemi.com 6 Theory of Operation This switching power supply is comprised of an inverted buck regulator controlled by a current mode, hysteretic control circuit. The buck regulator operates exactly like a conventional buck regulator except the power device placement has been inverted to allow for a low side power FET. Referring to Figure 1, when the FET is conducting, current flows from the input, through the inductor, the LED and the FET to ground. When the FET shuts off, current continues to flow through the inductor and LED, but is diverted through the diode (D1). This operation keeps the current in the LED continuous with a continuous current ramp. The control circuit controls the current hysteretically. Figure 2 illustrates the operation of this circuit. The CS comparator thresholds are set to provide a 10% current ripple. The peak current comparator threshold of 220 mV sets Ipeak at 10% above the average current while the valley current comparator threshold of 180 mV sets Ivalley at 10% below the average current. When the FET is conducting, the current in the inductor ramps up. This current is sensed by the sense resistor that is connected from CS to ground. When the voltage on the CS pin reaches 220 mV, the peak current comparator turns off the power FET. A conventional hysteretic controller would monitor the load current and turn the switch back on when the CS pin reaches 180 mV. But in this topology the current information is not available to the control circuit when the FET is off. To set the proper FET off time, the CS voltage is sensed when the FET is turned back on and a correction signal is sent to the off time circuit to adjust the off time as necessary. When the FET is turned on, there can be a lot of ringing on the CS pin that would make the voltage on the CS pin be an unreliable measure of the current through the FET. An 85 ns blanking timer is started when the GATE voltage starts to go high, to allow this ringing to settle down. At the end of this blanking timer, CS voltage is sensed to determine the valley current. Figure 4. Typical Current Waveforms The current wave shape is triangular, and the peak and valley currents are controlled. The average value for a triangular wave shape is halfway between the peak and valley, so even with changes in duty cycle due to input voltage variations or load changes, the average current will remain constant. Over Current Protection Feature In the event there is a short−circuit across the LEDs, a large amount of current could potentially flow through the circuit during startup. To protect against this, the NCL30161 comes with a short circuit protection feature. If the voltage on the CS pin is detected to be greater than the over current protection limit, the NCL30161 will turn off the FET, and prevent the FET from turning on again until power is recycled to the NCL30161. Undervoltage Lockout When VIN rises above the UVLO threshold voltage, switching operation of the FET will begin. However, until the VIN voltage reaches 8 V, the VCC regulator may not provide the expected gate drive voltage to the FET. This could result in the RDS(on) of the FET being higher than expected or there not being enough gate drive capability to operate at the maximum rated switching frequency. For optimal performance, it is recommended to operate the part at a VIN voltage of 8 V or greater. Setting The Output Current The average output current is determined as being the middle of the peak and valley of the output current, set by the CS comparator thresholds. The nominal average output current will be the current value equivalent to 200 mV at the CS pin. The proper RSENSE value for a desired average output current can be calculated by: RSENSE + 200 mV ILED PWM Dimming For a given RSENSE value, the average output current, and therefore the brightness of the LED, can be set to a lower value through the DIM/EN pin. When the DIM/EN pin is brought low, the internal FET will turn off and switching will remain off until the DIM/EN pin is brought back into its high state. By applying a pulsed signal to DIM/EN, the average output current can be adjusted to the duty ratio of the pulsed signal. It is recommended to keep the frequency of the DIM/EN signal above 100 Hz to avoid any visible flickering of the LED. |
Similar Part No. - NCL30161 |
|
Similar Description - NCL30161 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |