ATmega16 datasheet(249/315 Pages) ATMEL

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249

ATmega16(L)

2466E–AVR–10/02

See Table 95 and Table 96 for how the different settings of the Boot Loader bits affect

the Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed

if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in

SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is

recommended to load the Z-pointer with $0001 (same as used for reading the Lock

bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”

when writing the Lock bits. When programming the Lock bits the entire Flash can be

read during the operation.

EEPROM Write Prevents

Writing to SPMCR

Note that an EEPROM write operation will block all software programming to Flash.

Reading the Fuses and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the user checks the status bit (EEWE)

in the EECR register and verifies that the bit is cleared before writing to the SPMCR

Reading the Fuse and Lock

Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,

load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When

an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN

bits are set in SPMCR, the value of the Lock bits will be loaded in the destination regis-

ter. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock

bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is

executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will

work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low bits is similar to the one described above for

reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set

the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within

three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the

Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to

Table 105 on page 256 for a detailed description and mapping of the Fuse Low bits.

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination reg-

ister as shown below. Refer to Table 104 on page 255 for detailed description and

mapping of the Fuse High bits.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply volt-

age is too low for the CPU and the Flash to operate properly. These issues are the same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program corruption can be caused by two situations when the voltage is too low.

First, a regular write sequence to the Flash requires a minimum voltage to operate

Bit

543210

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

543

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

543

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

ATMEGA16 Datasheet(PDF) 249 Page - ATMEL Corporation

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