ATmega16 datasheet(269/315 Pages) ATMEL

269 / 315 page

269

ATmega16(L)

2466E–AVR–10/02

Chip Erase instruction. The Chip Erase operation turns the content of every memory

location in both the Program and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

High:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

SPI Serial Programming

Algorithm

When writing serial data to the ATmega16, data is clocked on the rising edge of SCK.

When reading data from the ATmega16, data is clocked on the falling edge of SCK. See

Figure 137 for timing details.

To program and verify the ATmega16 in the SPI Serial Programming mode, the follow-

ing sequence is recommended (See four byte instruction formats in Table 115):

Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In

some systems, the programmer can not guarantee that SCK is held low during

power-up. In this case, RESET must be given a positive pulse of at least two

CPU clock cycles duration after SCK has been set to “0”.

Wait for at least 20 ms and enable SPI Serial Programming by sending the Pro-

gramming Enable serial instruction to pin MOSI.

The SPI Serial Programming instructions will not work if the communication is

out of synchronization. When in sync. the second byte ($53), will echo back

when issuing the third byte of the Programming Enable instruction. Whether the

echo is correct or not, all four bytes of the instruction must be transmitted. If the

$53 did not echo back, give RESET a positive pulse and issue a new Program-

ming Enable command.

The Flash is programmed one page at a time. The memory page is loaded one

byte at a time by supplying the 6 LSB of the address and data together with the

Load Program Memory Page instruction. To ensure correct loading of the page,

the data low byte must be loaded before data high byte is applied for a given

address. The Program Memory Page is stored by loading the Write Program

Memory Page instruction with the 7 MSB of the address. If polling is not used,

the user must wait at least tWD_FLASH before issuing the next page. (See Table

114). Accessing the SPI Serial Programming interface before the Flash write

operation completes can result in incorrect programming.

The EEPROM array is programmed one byte at a time by supplying the address

and data together with the appropriate Write instruction. An EEPROM memory

location is first automatically erased before new data is written. If polling is not

used, the user must wait at least tWD_EEPROM before issuing the next byte. (See

Table 114). In a chip erased device, no $FFs in the data file(s) need to be

programmed.

Any memory location can be verified by using the Read instruction which returns

the content at the selected address at serial output MISO.

At the end of the programming session, RESET can be set high to commence

normal operation.

Power-off sequence (if needed):

Set RESET to “1”.

Turn VCC power off.

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