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LM7332 Datasheet(PDF) 21 Page - Texas Instruments |
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LM7332 Datasheet(HTML) 21 Page - Texas Instruments |
21 / 34 page ![]() LM7332 www.ti.com SNOSAV4B – APRIL 2008 – REVISED JANUARY 2016 Typical Application (continued) 8.2.2 Detailed Design Procedure The LM7332 can be used as a drive amplifier for SAR ADCs as shown in Figure 50. The values of Rflt and Cflt depend on the ADC specifications as well as amplifier gain bandwidth product (GBWP) and output resistance (RO). It is also common to have a single ground-referenced supply voltage and sample signals up to half of the supply voltage with low distortion. To determine whether or not the LM7332 is a suitable driver for this application, one must compare the settling time of the amplifier to the acquisition time of the ADC with Equation 1: GBWPmin ≥ 4 × (N+1) × ln(2) / (2π × tAQ) where • GBWPmin: The minimum required gain bandwidth product of the drive amplifier • N: Number of bits in ADC • tAQ: The acquisition time of the ADC (1) Using a value of 12 bits for N and 1µs for tAQ, the GBWPmin must be greater than 5.7 MHz. The LM7332 has a GBWP of 21 MHz so it is indeed a suitable driver for this application. Next, determine the value of Cflt with Equation 2: 20 × CSH ≤ Cflt ≤ 60 × CSH where • CSH: The ADC sample and hold capacitance • Cflt: The external filter capacitance (2) Using a value of 80 pF for CSH, the value of Cflt must be between 1600 pF and 4800 pF. According to Figure 39, the LM7332 can drive a capacitive load of 2000 pF with 5 VPP and settle within 1 µs, therefore select 1800 pF as the nearest common capacitor value within the range. Next determine the value of Rflt with Equation 3: Rflt = 40 / (2π × Cflt ×GBWPmin) – RO where • Rflt: The external filter resistance • Cflt: The external filter capacitance determined above • GBWPmin: The minimum required gain bandwidth product of the drive amplifier determined above • RO: The closed loop output impedance of the drive amplifier typically specified in the electrical characteristics table (3) Using a value of 1800 pF for Cflt, 5.7 MHz for GBWPmin, and a value of 3 Ω for RO the value of Rflt is determined to be 617.5 Ω. Use closest value of 620 Ω for a filter frequency (fflt) of 142 kHz given Equation 4: fflt=1 / (2π × (RO + Rflt) × Cflt) (4) The last requirement is to drive input signals of 2.5 VPP on a single 5-V supply with THD+N less than –80 dB. Figure 51 shows the THD+N response of the LM7332 with a single supply voltage of 5 V. The LM7332 can maintain THD+N levels as low as –83 dB for output levels up to 4 VPP. Therefore the final requirement has been met, and the LM7332 is a suitable drive amplifier for the 12-bit SAR ADC in this design example. Driving two independent channels of the SAR ADC within minimal crosstalk between the channels may also be required. Figure 52 shows the crosstalk rejection over frequency. The LM7332 achieves 105 dB of crosstalk rejection up to 20 kHz and greater than 75 dB up to 1MHz which demonstrates the suitability of measuring very large input signals without interfering with adjacent channels. Copyright © 2008–2016, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LM7332 |
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