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MEC1322 Datasheet(PDF) 251 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 251 Page - Microchip Technology |
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251 / 456 page ![]() 2014 - 2015 Microchip Technology Inc. DS00001719D-page 251 MEC1322 13:12 Mux Control The Mux Control field determines the active signal function for a pin. 00 = GPIO Function Selected 01 = Signal Function 1 Selected 10 = Signal Function 2 Selected 11 = Signal Function 3 Selected R/W Note 20-5 VCC1_R ESET 11 Polarity 0 = Non-inverted 1 = Inverted When the Polarity bit is set to ‘1’ and the Mux Control bits are greater than ‘00,’ the selected signal function outputs are inverted and Inter- rupt Detection (int_det) sense defined in Table 20-8, "Edge Enable and Interrupt Detection Bits Definition" is inverted. When the Mux Control field selects the GPIO signal function (Mux = ‘00’), the Polar- ity bit does not effect the output. Regardless of the state of the Mux Control field and the Polarity bit, the state of the pin is always reported without inversion in the GPIO input register. R/W Note 20-5 VCC1_R ESET 10 Output GPIO Write Enable Every GPIO has two mechanisms to set a GPIO data output: Output GPIO Bit located in the GPIO Output Registers and the Alternative GPIO data bit located in bit 16 of this register. This control bit determines the source of the GPIO output. 0 = Alternative GPIO data write enabled When this bit is zero the Alternative GPIO data write is enabled and the Output GPIO is disabled. 1 = Output GPIO enable When this bit is one the Alternative GPIO data write is disabled and the Output GPIO is enabled. Note: See description in Section 20.4, "Accessing GPIOs". R/W Note 20-5 VCC1_R ESET 9GPIO Direction 0 = Input 1 = Output The GPIO Direction bit controls the buffer direction only when the Mux Control field is ‘00’ selecting the pin signal function to be GPIO. When the Mux Control field is greater than ‘00’ (i.e., a non- GPIO signal function is selected) the GPIO Direction bit has no affect and the selected signal function logic directly controls the pin direc- tion. R/W Note 20-5 VCC1_R ESET Offset See Note 20-5 Bits Description Type Default Reset Event |
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