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MEC1322 Datasheet(PDF) 397 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 397 Page - Microchip Technology |
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397 / 456 page ![]() 2014 - 2015 Microchip Technology Inc. DS00001719D-page 397 MEC1322 38.0 TIMING DIAGRAMS 38.1 Voltage Thresholds and Power Good Timing 38.1.1 VCC1_RST# TIMING FIGURE 38-1: VCC1_RST# TIMING Note 38-1 The ARM starts executing instructions when EC_PROC_ RESET deasserts, which has the same timing as t3. FIGURE 38-2: VCC1_RST# RISE TIME Note 38-2 This corresponds to the time 2.65us (min) after the VCC1_RST# pin is released, the VCC1_RST# pin input is sampled. See Section 3.6.1, "Integrated Vcc1 Power On Reset (VCC1_RST#)," on page 53. Note: Timing values are preliminary and may change after characterization. TABLE 38-1: VCC1_RST# TIMING Parameters Symbol MIN TYP MAX Unit Notes VCC1 Threshold for Pin Glitch Protection active VTH1 0.9 1 1.1 V VCC1 Power Good Threshold VTH2 2.16 2.4 2.64 V VCC1 Rise Time (Off to VCC1 =VThreshold)VRise 200 μs VCC1 Fall Time (VCC1 =VThreshold) to Off VFall 200 μs VCC1 > VTH2 to VCC1GD (internal) asserted t1 600 μs VCC1 < VTH2 to VCC1GD (internal) deas- serted and VCC1_RST# pin asserted t2 100 ns VCC1 > VTH2 to VCC1_RST# pin deasserted t3 1 ms Note 38-1 TABLE 38-2: VCC1_RST# RISE TIME Parameters Symbol MIN TYP MAX Units Notes VCC1_RST# Rise Time t1 2.65 μs Note 38-2 U ndefin ed F unc tional t1 F o rc ed to lo gic ‘0 ’ F o rc ed to lo gic ‘0 ’ V CC1 G D (in te r n a l) G litc h pr ote c te d S ig n a l output V CC1 U ndefined t2 V TH 2 V TH 2 V TH 1 V TH 1 VC C 1 _ R ST # Pin t3 V CC1 _ R S T # P in t1 |
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