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PI3546-00-LGIZ Datasheet(PDF) 25 Page - Vicor Corporation |
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PI3546-00-LGIZ Datasheet(HTML) 25 Page - Vicor Corporation |
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25 / 37 page  Cool-Power® Rev 1.3 vicorpower.com Page 25 of 37 02/2016 800 927.9474 PI354x-00 Output Overvoltage Protection The PI354x-00 family is equipped with output Overvoltage Protection (OVP) to prevent damage to input voltage sensitive devices. If the output voltage exceeds 20% of its set regulated value, the regulator will complete the current cycle and stop switching. The system will resume operation once the output voltage falls below the OVP threshold and after Fault Restart Delay. Overtemperature Protection The internal package temperature is monitored to prevent internal components from reaching their thermal maximum. If the Overtemperature Protection Threshold (OTP) is exceeded (TOTP), the regulator will complete the current switching cycle, enter a low power mode and will soft-start when the internal temperature falls below Over-Temperature Restart Hysteresis (TOTP_HYS). Pulse Skip Mode (PSM) PI354x-00 features a PSM to achieve high efficiency at light loads. The regulators are setup to skip pulses if EAO falls below a PSM threshold. Depending on conditions and component values, this may result in single pulses or several consecutive pulses followed by skipped pulses. Skipping cycles significantly reduces gate drive power and improves light load efficiency. The regulator will leave PSM once the EAO rises above the Skip Mode threshold. Variable Frequency Operation Each PI354x-00 is preprogrammed to a base operating frequency, with respect to the power stage inductor (see Table 2), to operate at peak efficiency across line and load variations. At low line and high load applications, the base frequency will decrease to accommodate these extreme operating ranges. By stretching the frequency, the ZVS operation is preserved throughout the total input line voltage range therefore maintaining optimum efficiency. Parallel Operation Paralleling modules can be used to increase the output current capability of a single power rail and when interleaved, reduce output voltage ripple. The PI354x-00 can support a maximum number of two interleaved modules. A higher number of modules (up to six maximum) may be connected in parallel without interleaving or synchronization. A user may connect three groups of two phase interleaved modules together, for example. By connecting the EAO pins and SGND pins of each module together the units will share the current equally, independent of synchronization or interleaving. When the TRK pins of each unit are connected together, the units will track each other during soft-start. All units EN pins have to be released together to allow the units to start (See Figure 50). A fault event occurring in any regulator will disable the other regulators. To provide synchronization between regulators over a limited operational frequency range, the Power Good (PGD) pin must be connected to the lead regulator’s (#1) SYNCI pin and a 2.4 kΩ Resistor, R1, must be placed between SYNCO (#2) return and the lead regulator’s SYNCI (#1) pin, as shown in Figure 50. In this configuration, at system soft-start, the PWRGD pin pulls SYNCI low forcing the lead regulator to initialize the open-loop startup synchronization. Once the regulators reach regulation, SYNCI is released and the system is now synchronized in a closed-loop configuration which allows the system to adjust, on the fly, when any of the individual regulators begin to enter variable frequency mode in the loop. The closed loop method is effective in maintaining synchronization if the switching frequency varies to 75% of each regulators programmed switching frequency. If the application requires synchronization over a wider range, please contact Applications Support. Application Description Output Voltage Set Point The PI354x-00 family of Buck Regulators utilizes an internal 1 V reference. The output voltage setting is accomplished using external resistors as shown in Figure 51. Select R2 to be at or around 1 k for best noise immunity. Use equations (1) and (2) to determine the proper value based on the desired output voltage. Figure 50 — PI354x-00 parallel operations Vin Vout Cin Cout L1 (#1) VOUT VS1 LGH TRK EAIN EAO COMP VSN VSP VDIFF PI354X EN VIN SYNCI PGND SYNCO PWRGD TESTx VDR SGND Vin Cin Cout L1 (#2) VOUT VS1 LGH TRK EAIN EAO COMP VSN VSP VDIFF PI354X EN VIN SYNCI PGND SYNCO PWRGD TESTx VDR SGND R1 SYNCO #2 SYNCI #2 EN #2 SYNCO #1 EN #1 EAO #1 TRK #2 TRK #1 To R1 EAO #2 Figure 51 — External resistor divider network EAO EAIN + - Vref COMP + - 100mV LGH Vout Rzi Chf R1 R2 |
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