ST7MC2 datasheet(204/308 Pages) STMICROELECTRONICS

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MOTOR CONTROLLER (Cont’d)

10.6.10.5 Repetition Down-Counter

Both in center-aligned and edge-aligned modes,

the four Compare registers (one Compare 0 and

three for the U, V and W phases) are updated

when the PWM counter underflow or overflow and

the 8-bit Repetition down-counter has reached ze-

ro.

This means that data are transferred from the

preload compare registers to the compare regis-

ters every N cycles of the PWM Counter, where N

is the value of the 8-bit Repetition register in edge

-aligned mode. When using center-aligned mode,

the repetition down-counter is decremented every

time the PWM counter overflows or underflows. Al-

though this limits the maximum number of repeti-

tion to 128 PWM cycles, this makes it possible to

update the duty cycle twice per PWM period. As a

result, the effective PWM resolution in that case is

equal to the resolution we can get using edge-

aligned mode, i.e. one Tmtc period. When refresh-

ing compare registers only once per PWM period

in center-aligned mode, maximum resolution is

2xTmtc , due to the symmetry of the pattern.

The repetition down counter is an auto-reload

type; the repetition rate will be maintained as de-

fined by the MREP register value (refer to Figure

122).

10.6.10.6 PWM interrupt generation

A PWM interrupt is generated synchronously with

the “U” update event, which allows to refresh com-

pare values by software before the next update

event. As a result, the refresh rate for phases duty

cycles is directly linked to MREP register setting.

A signal reflecting the update events may be out-

put on a standard I/O port for debugging purposes.

Refer to section10.6.7.3 on page 171 for more de-

tails.

Figure 122. Update rate examples depending on mode and MREP register settings

Center-aligned mode

Edge-aligned mode

U Event: Preload registers transferred to active registers and PWM interrupt generated

12-bit PWM

Counter

MREP = 0

MREP = 1

MREP = 2

MREP = 3

U Event if transition from MREP = 0 to MREP = 1 occurs when 12-bit counter is equal

to MCP0.

MREP = 3

and

re-synchronization

(by SW)

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