ST92185B2 datasheet(164/178 Pages) STMICROELECTRONICS

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ST92185B - PWM GENERATOR

PWM GENERATOR (Cont’d)

AUTOCLEAR REGISTER (ACR)

R248 - Read/Write

Reset Value: 1111 1111 (FFh)

This register behaves exactly as a 9th compare

rate.

The reset condition generates the free running

mode. So, FFh means count by 256.

Bit 7:0 = AC[7:0]:

Autoclear Count Value.

When 00 is written to the Compare Register, if the

ACR register = FFh, the PWM output bit is always

set except for the last clock count (255 set and 1

reset; the converse when the output is comple-

mented). If the ACR content is less than FFh, the

PWM output bit is set for a number of clock counts

equal to that content (see Figure 2).

Writing the Compare register constant equal to the

ACR register value causes the output bit to be al-

ways reset (or set if complemented).

Example: If 03h is written to the Compare Regis-

ter, the output bit is reset when the CRR counter

reaches the ACR register value and set when it

reaches the Compare register value (after 4 clock

counts, see Figure 3). The action will be reversed

if the output is complemented. The PWM mark/

space ratio will remain constant until changed by

software writing a new value in the ACR register.

COUNTER REGISTER (CRR)

R249 - Read Only

Reset Value: 0000 0000 (00h)

This read-only register returns the current counter

value when read.

The 8 bit Counter is initialized to 00h at reset, and

is a free running UP counter.

Bit 7:0 = CR[7:0]:

Current Counter Value.

PRESCALER

AND

CONTROL

(PCTL)

R250 - Read/Write

Reset Value: 0000 1100 (0Ch)

Bit 7:4 = PR[3:0]

PWM Prescaler value.

These bits hold the Prescaler preset value. This is

reloaded into the 4-bit prescaler whenever the

prescaler (DOWN Counter) reaches the value 0,

so determining the 8-bit Counter count frequency.

The value 0 corresponds to the maximum counter

frequency which is INTCLK/2. The value Fh corre-

sponds to the maximum frequency divided by 16

(INTCLK/32).

The reset condition initializes the Prescaler to the

Maximum Counter frequency.

Bit 3:2 = Reserved. Forced by hardware to “1”

Bit 1 = CLR:

Counter Clear.

This bit when set, allows both to clear the counter,

and to reload the prescaler. The effect is also to

clear the PWM output. It returns “0” if read.

Bit 0 = CE:

Counter Enable.

This bit enables the counter and the prescaler

when set to “1”. It stops both when reset without

affecting their current value, allowing the count to

be suspended and then restarted by software “on

fly”.

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

PR3

PR2

PR1

PR0

CLR

PR[3:0]

Divider Factor

Frequency

INTCLK/2 (Max.)

INTCLK/4

INTCLK/6

INTCLK/32 (Min.)

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