LAN8740 datasheet(131/136 Pages) MICROCHIP

131 / 136 page

 2013-2015 Microchip Technology Inc.

DS00001987A-page 131

LAN8740A/LAN8740Ai

Rev. 1.1

(05-10-13)

Section 4.3, "MDIO Manageable Device

(MMD) Registers"

Added additional vendor specific MMD register

descriptions

Section 4.3.11, "MAC Receive Address

A Register (RX_ADDRA)"

Added note

Section 4.3.12, "MAC Receive Address

B Register (RX_ADDRB)"

Added note

Section 4.3.13, "MAC Receive Address

C Register (RX_ADDRC)"

Added note

, "," on page 113

Removed section “Power Sequence Timing”

Section 5.1, "Absolute Maximum

Ratings*"

Changed: Positive voltage on XTAL1/CLKIN, with

respect to ground from “VDDCR” to “+3.6V”

Section 5.3, Table 5-1, “Package

Thermal Parameters”

Updated package thermal specification values

Section 5.4, "Power Consumption"

Updated power numbers

Section 5.5, "DC Specifications"

Changed VIHI max of ICLK Type Buffer from

“VDDCR” to “3.6”

Section 5.6, "AC Specifications"

Removed two RMII notes at beginning of section

Section 5.6.3.1, "100 Mbps Internal

Loopback MII Timing"

Added new 100 Mbps internal loopback timing

section and diagram

Section 5.6.4, "RMII Interface Timing"



Added note detailing CRS_DV behavior as both

carrier sense and data valid



Updated RMII timing table

Rev. 1.0

(05-11-12)

Initial Release

REVISION LEVEL

& DATE

SECTION/FIGURE/ENTRY

CORRECTION

LAN8740 Datasheet(PDF) 131 Page - Microchip Technology

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