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WM8281ECS/R Datasheet(PDF) 127 Page - Cirrus Logic

Part # WM8281ECS/R
Description  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Datasheet(HTML) 127 Page - Cirrus Logic

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WM8281
Rev 4.0
127
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4865
(1301h)
DSP3
Clocking 1
2:0
DSP3_CLK_SEL
[2:0]
000
DSP3 Clock Frequency Select
000 = 6.144MHz (5.6448MHz)
001 = 12.288MHz (11.2896MHz)
010 = 24.576MHz (22.5792MHz)
011 = 49.152MHz (45.1584MHz)
100 = 73.728MHz (67.7376MHz)
101 = 98.304MHz (90.3168MHz)
110 = 147.456MHz (135.4752MHz)
111 = Reserved
The DSP3 Clock must be less than or
equal to the SYSCLK frequency. The
frequencies must also be integer-related
(eg. divide by 1, 2, 3 etc.).
The frequencies in brackets apply for
44.1kHz-related sample rates only (ie.
SAMPLE_RATE_n = 01XXX).
R4868
(1304h)
DSP3
Status 1
0
DSP3_RAM_RD
Y
0
DSP3 Memory Status
0 = Not ready
1 = Ready
Note - DSP3 memory should not be
accessed until this bit has been set.
R4870
(1306h)
DSP3
Status 3
3:1
DSP3_CLK_SEL
_STS [2:0
000
DSP3 Clock Frequency
(Read only, Only valid when the
respective DSP Clock is enabled)
000 = 6.144MHz (5.6448MHz)
001 = 12.288MHz (11.2896MHz)
010 = 24.576MHz (22.5792MHz)
011 = 49.152MHz (45.1584MHz)
100 = 73.728MHz (67.7376MHz)
101 = 98.304MHz (90.3168MHz)
110 = 147.456MHz (135.4752MHz)
111 = Reserved
The frequencies in brackets apply for
44.1kHz-related sample rates only (ie.
SAMPLE_RATE_n = 01XXX).
0
DSP3_CLK_AVAI
L
0
DSP3 Clock Availability
(Read only)
0 = No Clock
1 = Clock Available
Note
– this bit exists for legacy software
support only; it is not recommended for
future designs, as the readback may be
unreliable on the latest device
architectures.
R4871
(1307h)
DSP3
Status 4
15:0
DSP3_DUALME
M_COLLISION_A
DDR [15:0]
0000h
DSP3 Dual Memory Collision Address
In the event of a DSP3 memory access
collision, this field will report the address
at which the collision occurred.
The address is defined relative to the base
address of the shared data memory. The
LSB represents one 24-bit DSP memory
word.



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