PC97307VUL datasheet(120/218 Pages) NSC

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120

Parallel Port (Logical Device 4)

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6.5

ECP MODE REGISTERS

The ECP registers are each a byte wide, and are listed in

Table 6-6 in order of their offsets from the base address of

the parallel port. In addition, the ECP has control registers

at second level offsets, that are accessed via the EIR and

EDR registers. See Section 6.5.2 on page 120.

TABLE 6-6. Extended Capabilities Parallel Port (ECP)

Registers

Offset

Symbol

Description

Modes

(ECR Bits)

7 6 5

R/W

000h

DATAR

Parallel Port Data

0 0 0

0 0 1

R/W

000h

AFIFO

ECP Address FIFO

0 1 1

001h

DSR

Status Register

All Modes

002h

DCR

Control Register

All Modes

R/W

400h

CFIFO

Parallel Port Data

FIFO

0 1 0

400h

DFIFO

ECP Data FIFO

0 1 1

R/W

400h

TFIFO

Test FIFO

1 1 0

R/W

400h

CNFGA

Conﬁguration

1 1 1

401h

CNFGB

Conﬁguration

1 1 1

402h

ECR

Extended Control

All Modes

R/W

403h

EIR

Extended Index

All Modes

R/W

404h

EDR

Extended Data

All Modes

R/W

405h

EAR

Extended Auxiliary

Status Register

All Modes

R/W

Control Registers at Second Level Offsets

00h

Control0

All Modes

R/W

02h

Control2

All Modes

R/W

04h

Control4

All Modes

R/W

05h

PP Confg0

All Modes

R/W

6.5.1

Accessing the ECP Registers

The AFIFO, CFIFO, DFIFO and TFIFO registers access the

same ECP FIFO. The FIFO is accessed at Base + 000h, or

Base + 400h, depending on the mode field of ECR and the

The FIFO can be accessed by system DMA cycles, as well

as system PIO cycles.

When the DMA is configured and enabled (bit 3 of ECR is 1

and bit 2 of ECR is 0) the ECP automatically (by hardware)

issues DMA requests to fill the FIFO (in the forward direc-

tion when bit 5 of DCR is 0) or to empty the FIFO (in the

backward direction when bit 5 of DCR is 1). All DMA trans-

fers are to or from these registers. The ECP does not assert

DMA requests for more than 32 consecutive DMA cycles.

The ECP stops requesting the DMA when TC is detected

during an ECP DMA cycle.

A “Demand DMA” feature reduces system overhead

caused by DMA data transfers. When this feature is en-

abled by bit 6 of the PP Config0 register at second level off-

set 05h, it prevents servicing of DMA requests until after

four have accumulated and are held pending. See “Bit 6 -

Demand DMA Enable” on page 128.

Writing into a full FIFO, and reading from an empty FIFO,

are ignored. The written data is lost, and the read data is un-

defined. The FIFO empty and full status bits are not affected

by such accesses.

Some registers are not accessible in all modes of operation,

or may be accessed in one direction only. Accessing a non

accessible register has no effect. Data read is undefined;

data written is ignored; and the FIFO does not update. The

SPP registers (DTR, STR and CTR) are not accessible

when the ECP is enabled.

To improve noise immunity in ECP cycles, the state ma-

chine does not examine the control handshake response

lines until the data has had time to switch.

In ECP modes:

• DATAR replaces DTR of SPP/EPP

• DSR replaces STR of SPP/EPP

• DCR replaces CTR of SPP/EPP

6.5.2

Second Level Offsets

The EIR, EDR, and EAR registers support enhanced con-

trol and status features. When bit 4 of the Parallel Port Con-

figuration register is 1 (as described in Section 2.7.1 on

page 37), EIR and EDR serve as index and data registers,

respectively.

EIR and EDR at offsets 403 and 404, respectively, access

the control registers (Control0, Control2, Control4 and PP

Config0) at second level offsets 00h, 02h, 04h and 05h, re-

spectively. These control registers are functional only. Ac-

cessing these registers is possible when bit 4 of the

SuperI/O Parallel Port Configuration register at index F0h of

logical device 4 is1 and when bit 2 or 10 of the base address

is 1.

PC97307VUL Datasheet(PDF) 120 Page - National Semiconductor (TI)

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