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8S003F3P6 Datasheet(PDF) 66 Page - STMicroelectronics |
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8S003F3P6 Datasheet(HTML) 66 Page - STMicroelectronics |
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66 / 104 page  Electrical characteristics STM8S003F3 STM8S003K3 66/104 DocID018576 Rev 9 9.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 38. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage VDD = 5 V -0.3 - 0.3 x VDD V VIH Input high level voltage 0.7 x VDD -VDD + 0.3 V V Vhys Hysteresis(1) -700 - mV Rpu Pull-up resistor VDD = 5 V, VIN = VSS 30 55 80 k Ω tR, tF Rise and fall time (10% - 90%) Fast I/Os Load = 50 pF -- 20(2) ns Standard and high sink I/Os Load = 50 pF - - 125(2) ns Ilkg Input leakage current, analog and digital VSS ≤ VIN ≤ VDD -- ±1 µA Ilkg ana Analog input leakage current VSS ≤ VIN ≤ VDD -- ±250 (3) nA Ilkg(inj) Leakage current in adjacent I/O Injection current ±4 mA - - ±1(3) µA 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results. 2. Data guaranteed by design. 3. Data based on characterization results. |
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