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8S003F3P6 Datasheet(PDF) 13 Page - STMicroelectronics |
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8S003F3P6 Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 104 page  DocID018576 Rev 9 13/104 STM8S003F3 STM8S003K3 Product overview 29 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real- time by means of shadow registers. • R/W to RAM and peripheral registers in real-time • R/W access to all resources by stalling the CPU • Breakpoints on all program-memory instructions (software breakpoints) • Two advanced breakpoints, 23 predefined configurations 4.3 Interrupt controller • Nested interrupts with three software priority levels • 32 interrupt vectors with hardware priority • Up to 27 external interrupts on six vectors including TLI • Trap and reset interrupts 4.4 Flash program memory and data EEPROM • 8 Kbyte of Flash program single voltage Flash memory • 128 byte true data EEPROM • User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2. |
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