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8S003F3P6 Datasheet(PDF) 50 Page - STMicroelectronics |
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8S003F3P6 Datasheet(HTML) 50 Page - STMicroelectronics |
50 / 104 page ![]() Electrical characteristics STM8S003F3 STM8S003K3 50/104 DocID018576 Rev 9 Table 20. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2 - ∞ µs/V VDD fall time rate(1) 1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min) when the tTEMP delay has elapsed. -2 - ∞ tTEMP Reset release delay VDD rising - - 1.7 ms VIT+ Power-on reset threshold -2.6 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8 V VHYS(BOR) Brown-out reset hysteresis -- 70 - mV |
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