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S3C72G9 Datasheet(PDF) 56 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 56 Page - Samsung semiconductor |
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56 / 96 page  ' -!(!%2 '!!-$ IRET Operation: Operand Operation Summary Bytes Cycles - Return from interrupt 1 3 Description: IRET is used at the end of an interrupt service routine. It pops the PC values successively from the stack and restores them to the program counter. The stack pointer is incremented by six and the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also automatically restored to their pre-interrupt values. Program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. If a lower-level or same-level interrupt was pending when the IRET was executed, IRET will be executed before the pending interrupt is processed. Since the 15th bit of an interrupt start address is not loaded in the PC when the interrupt is occured, this bit of PC values is always interpreted as a logic zero at that time. The start address of an interrupt in the ROM must for this reason be located in 0000H-3FFFH. Operand Binary Code Operation Notation - 1 1 0 1 0 1 0 1 PC14-8 ← (SP + 1) (SP) PC7-0 ← (SP + 3) (SP + 2) PSW ← (SP + 5) (SP + 4) SP ← SP + 6 Example: The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location 0123H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively. The instruction IRET leaves the stack pointer with the value 00H and the program returns to continue execution at location 0123H. During a return from interrupt, data is popped from the stack to the program counter. The data in stack locations 0FFH-0FAH is organized as follows: SP → (0FAH) PC11 - PC8 SP + 1 (0FBH) 0 PC14 PC13 PC12 SP + 2 (0FCH) PC3 - PC0 SP + 3 (0FDH) PC7 - PC4 SP + 4 (0FEH) IS1 IS0 EMB ERB SP + 5 (0FFH) C SC2 SC1 SC0 SP + 6 (00H) |
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