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S3C72G9 Datasheet(PDF) 58 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 58 Page - Samsung semiconductor |
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58 / 96 page  5-2$0 %! 1 JPS dst Operation: Operand Operation Summary Bytes Cycles ADR Jump direct in page (12 bits) 2 2 Description: JPS causes an unconditional branch to the indicated address with the 4 K byte program memory address space. Bits 0-11 of the program counter are replaced with the directly specified address. The destination address for this jump is specified to the assembler by a label or by an actual address in program memory. Operand Binary Code Operation Notation ADR 1 0 0 1 a11 a10 a9 a8 PC14-0 ← PC14-12+ADR11-0 a7 a6 a5 a4 a3 a2 a1 a0 Example: The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction JPS SUB at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS instruction jumps to the address in the block in which the instruction is located. If the first byte of the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or 0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program malfunction. |
Similar Part No. - S3C72G9 |
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Similar Description - S3C72G9 |
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