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S3C72G9 Datasheet(PDF) 62 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 62 Page - Samsung semiconductor |
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62 / 96 page  % LD dst,src Operation: Operand Operation Summary Bytes Cycles A,#im Load 4-bit immediate data to A 1 1 A,@RRa Load indirect data memory contents to A 1 1 A,DA Load direct data memory contents to A 2 2 A,Ra Load register contents to A 2 2 Ra,#im Load 4-bit immediate data to register 2 2 RR,#imm Load 8-bit immediate data to register 2 2 DA,A Load contents of A to direct data memory 2 2 Ra,A Load contents of A to register 2 2 EA,@HL Load indirect data memory contents to EA 2 2 EA,DA Load direct data memory contents to EA 2 2 EA,RRb Load register contents to EA 2 2 @HL,A Load contents of A to indirect data memory 1 1 DA,EA Load contents of EA to data memory 2 2 RRb,EA Load contents of EA to register 2 2 @HL,EA Load contents of EA to indirect data memory 2 2 Description: The contents of the source are loaded into the destination. The source's contents are unaffected. If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two times in succession, only the first LD will be executed; the other similar instructions that immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect' (see examples below). Operand Binary Code Operation Notation A,#im 1 0 1 1 d3 d2 d1 d0 A ← im A,@RRa 1 0 0 0 1 i2 i1 i0 A ← (RRa) A,DA 1 0 0 0 1 1 0 0 A ← DA a7 a6 a5 a4 a3 a2 a1 a0 A,Ra 1 1 0 1 1 1 0 1 A ← Ra 0 0 0 0 1 r2 r1 r0 Ra,#im 1 1 0 1 1 0 0 1 Ra ← im d3 d2 d1 d0 1 r2 r1 r0 |
Similar Part No. - S3C72G9 |
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Similar Description - S3C72G9 |
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