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S3C72G9 Datasheet(PDF) 67 Page - Samsung semiconductor |
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S3C72G9 Datasheet(HTML) 67 Page - Samsung semiconductor |
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67 / 96 page  % LDB (Continued) Examples: 1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following instruction clears the carry flag to logic zero. LDB C,P1.0 2. The P1 address is FF1H and the L register contains the value 1H (0001B). The address (memb.7-2) is 111100B and (L.3-2) is 00B. The resulting address is 11110000B or FF0H and P0 is addressed. The bit value (L.1-0) is specified as 01B (bit 1). LD L,#0001B LDB C,P1.@L ; P1.@L specifies P0.1 and C ← P0.1 3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for FLAG(3-0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value is 3. Therefore, @H+FLAG = 20H.3. FLAG EQU 20H.3 LD H,#2H LDB C,@H+FLAG ; C ← FLAG (20H.3) 4. The following instruction sequence sets the carry flag and the loads the "1" data value to the output pin P1.0, setting it to output mode: SCF ; C ← "1" LDB P1.0,C ; P1.0 ← "1" 5. The P1 address is FF1H and L = 01H (0001B). The address (memb.7-2) is 111100B and (L.3- 2) is 00B. The resulting address, 11110000B specifies P0. The bit value (L.1-0) is specified as 01B (bit 1). Therefore, P1.@L = P0.1. SCF ; C ← "1" LD L,# 0001B LDB P1.@L,C ; P1.@L specifies P0.1 ; P0.1 ← "1" 6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit value is 3, @H+FLAG = 20H.3: FLAG EQU 20H.3 RCF ; C ← "0" LD H,#2H LDB @H+FLAG,C ; FLAG(20H.3) ← "0" , # 9 6: |
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